1. Field of the Invention
The present invention relates to a capacitor structure of a semiconductor memory cell using a ferroelectric thin film and a fabrication process thereof, and particularly to a capacitor structure of a nonvolatile semiconductor memory cell (so-called FERAM) or DRAM using a ferroelectric thin film and a fabrication process thereof.
2. Description of the Related Art
In recent years, with advance of the film formation technique, applied researches have been extensively made on nonvolatile semiconductor memories using ferroelectric thin films. The nonvolatile semiconductor memory allows high speed rewriting by making use of high speed polarization reversal and its residual polarization of a ferroelectric thin film. The nonvolatile semiconductor memories including ferroelectric thin films, which are being studied at present, are classified into a type of detecting the amount of electric charges stored in a ferroelectric capacitor portion and a type of detecting a change in resistance of a semiconductor due to spontaneous polarization of a ferroelectric material. The semiconductor memory cell, to which the present invention is applied, is the former type.
The nonvolatile semiconductor memory cell of the type of detecting a change in the amount of electric charges stored in a ferroelectric capacitor portion, is basically composed of a ferroelectric capacitor portion and a selective transistor. The ferroelectric capacitor portion typically includes a lower electrode, an upper electrode, and a capacitor thin film composed of a ferroelectric thin film which is held therebetween and has a relatively high dielectric constant .epsilon.. Writing and reading of data in and from the nonvolatile semiconductor memory cell of this type are performed using a P-E hysteresis loop of a ferroelectric material shown in FIG. 13. When an external electric field is applied to a ferroelectric thin film and then removed therefrom, the ferroelectric thin film exhibits a spontaneous polarization. When being applied with a positive external electric field, the ferroelectric thin film exhibits a residual polarization+Pr. Besides, when being applied with a negative external electric field, the ferroelectric thin film exhibits a residual polarization-Pr. Here, the case where the ferroelectric thin film exhibits the residual polarization+Pr (see a state "D" of FIG. 13) is taken as "0", and the case where it exhibits the residual polarization-Pr (see a state "A" of FIG. 13) is taken as "1".
To identify the state "1" or "0", for example, a positive external electric field is applied to the ferroelectric thin film. The ferroelectric thin film thus applied with the positive electric field exhibits a polarization shown by character C of FIG. 13. At this time, if the data is "0", the polarization state of the ferroelectric thin film is changed from the state "D" to "C". On the other hand, if the data is "1", the polarization state of the ferroelectric thin film is changed from the state "A" to "C" by way of "B". That is, if the data is "0", the ferroelectric thin film does not exhibit any polarization reversal. On the other hand, if the data is "1", it exhibits the polarization reversal. As a result, there occurs a difference in the amount of electric charges stored in the ferroelectric capacitor portion. Thus, the stored electric charges are detected as a signal current by turning on the selective transistor of the selected memory cell. When the external electric field is made zero after read-out of the data, the polarization state of the ferroelectric thin film becomes the state "D" of FIG. 13 even if the state is "0" or "1". Accordingly, in the case where the data is "1", the data "1" is written by applying a negative external electric field to change the state "D" to "A" by way of "E".
Capacitor structures of a type in which a lower electrode is provided on a buffer layer formed of Ti on a SiO.sub.2 layer; a capacitor thin film is made from Pb(Zr.sub.1-y, Ti.sub.y)O.sub.3 ; and an upper electrode is made from Pt (platinum), are known, for example, from Ramton Corporation, "FRAM Cell", Thomas Boehm, HE6-94-2001; "Polarization Fatigue Characteristics of Sol-Gel Ferroelectric Pb(Zr.sub.0.4 Ti.sub.0.6)O.sub.3 Thin-Film Capacitors", T. Mihama, et al., Jpn. J. Appl. Phys. Vol. 33 (1994), pp 3996-4002; "Fatigue Characteristics of Sol-Gel Derived Pb (Zr, Ti)O.sub.3 Thin Films", K. Amanuma, et al., Jpn. J. Appl. Phys. Vol. 33 (1994), pp 5211-5214; and "Low-temperature Preparation Of Pb(Zr, Ti)O.sub.3 Thin Film", I. Kanno. et al., Jpn. J. Appl. Phys. Vol. 32 (1993), pp 4057-4060. Further, capacitor structures of a type in which a capacitor thin film is made from SrBi.sub.2 Ta.sub.2 O.sub.9 in place of Pb(Zr.sub.1-y, Ti.sub.y)O.sub.3, are known, for example, from WO93/12542, "Preparation and ferroelectric properties of SrBi.sub.2 Ta.sub.2 O.sub.9 thin film", K. Amanuma, et al., Appl. Phys. Lett. 66(2), Jan. 9, 1995; and "A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 10 ns", ISSC 94, PP 268. The use of Ru (ruthenium) added with a trace of oxygen as an electrode material is known from "Application of Ru film added with trace oxygen to BST film capacitor electrode" (Proceedings No. 2 of the 57th Meeting of Jpn. Soc. of Appl. Phys., 8p-H-18).
A process of fabricating a semiconductor memory cell generally includes various heat-treatment steps performed at a hydrogen gas atmosphere at temperatures in a range of 280 to 450.degree. C. In such a heat-treatment, hydrogen gas may permeate an upper electrode. From this viewpoint, one example of a process of fabricating a semiconductor memory cell will be briefly described with reference to FIGS. 14A and 14B and FIG. 15 which typically show the partial cross-section of a semiconductor substrate and the like.
The description will be made of a so-called planar type volatile semiconductor memory cell including a MOS transistor element as a selective transistor and a capacitor structure (ferroelectric capacitor portion). The capacitor structure includes a lower electrode 22, a capacitor thin film 23 composed of a ferroelectric thin film formed on the lower electrode 22, and an upper electrode 24 formed on the capacitor thin film 23. The lower electrode 22 is electrically connected to one source/drain region 15 of the MOS transistor element through a contact plug 26A and an interconnection 29. The upper electrode 24 is connected to a plate line 28. The other source/drain region 15 of the MOS transistor element is connected to a bit line 30.
The MOS transistor is formed on a semiconductor substrate 10 in accordance with a known process, and a multi-layered interlayer insulating film 20 having, for example, a SiN layer, a BPSG layer, and a NSG layer, is formed over the entire surface by CVD. In the figures, the interlayer insulating film 20 having the multi-layered structure is shown as that having a single layer structure for simplification. A buffer layer 21 made from Ti, a lower electrode layer made from Pt, a ferroelectric thin film, and an upper electrode layer made from Pt are sequentially formed on the interlayer insulating film 20, and the upper electrode layer, ferroelectric thin film, lower electrode layer, and buffer layer are patterned, to form a capacitor structure shown in FIG. 14A. The ferroelectric thin film is made from a material expressed by EQU Bi.sub.x Sr.sub.y Ta.sub.2 O.sub.d (2)
where 1.7.ltoreq.X.ltoreq.2.5, 0.6.ltoreq.Y.ltoreq.1.2, and 8.0.ltoreq.d.ltoreq.10.0. In the figure, reference numeral 11 indicates an isolation region, 12 is a gate oxide film, 13 is a gate electrode, and 14 is a gate oxide wall.
A multi-layered insulating film 25, having a SiO.sub.2 layer formed using TEOS by plasma CVD, O.sub.3 -NSG layer, and a SiO.sub.2 layer formed using TEOS by plasma CVD, is formed. In the figures, the insulating layer 25 is shown as that having a single layer structure for simplification. The atmosphere for forming the SiO.sub.2 layer using TEOS by plasma CVD is a hydrogen rich atmosphere, and in this step, the semiconductor substrate is heated at about 400.degree. C. Next, openings 26 are formed in the insulating film 25 and the interlayer insulating layer 20 at positions over the source/drain region 15 of the MOS transistor by RIE (see FIG. 14B). To reduce a trap density at a SiO.sub.2 /Si interface of the MOS transistor, the semiconductor substrate is annealed in a forming gas composed of a mixed gas of N.sub.2 gas/H.sub.2 gas (5 vol %) at a temperature of 400 to 450.degree. C. At this time, hydrogen gas permeates the upper electrode 24 made from Pt through the insulating film 25, and further it permeates the capacitor film 23.
Openings 27 are formed in a portion of the insulating film 25 over the lower electrode 22 extending from the capacitor structure and also in a portion of the insulating film 25 over the upper electrode 24. A metal interconnection layer is formed by sputtering over the entire surface including the interiors of the openings 26 and 27, and is patterned to form the plate line 28, interconnection 29, and bit line 30 (see FIG. 15). Finally, a passivation film made from SiN is formed over the entire surface by plasma CVD. The concentration of hydrogen gas in the atmosphere used for formation of the. passivation film is 15-30 vol %, and in this step, the semiconductor substrate is heated at a temperature of 280 to 350.degree. C.
The upper electrode 24 made from Pt is damaged by the heat-treatments in the hydrogen gas atmosphere used for film formation by various CVD processes and for annealing in the forming gas. It is to be noted that the annealing in the forming gas is sometimes referred to simply to "annealing" hereinafter. The reason why the upper electrode 24 is damaged is that hydrogen gas, which has permeated the upper electrode 24 and further reached the capacitor thin film 23 formed of the ferroelectric thin film, reacts with oxygen atoms constituting the ferroelectric thin film, and thereby Bi atoms of the ferroelectric thin film made from Bi.sub.x St.sub.y Ta.sub.2 O.sub.d expressed in the equation (2) react with hydrogen to produce H.sub.2 O, as a result of which the upper electrode 24 made from Pt is damaged due to the attack of H.sub.2 O.
FIGS. 16A and 16B each show the result of microscopically observing a surface of an upper electrode of a capacitor structure provided on a buffer layer formed of Ti on an interlayer insulating film made from SiO.sub.2, wherein FIG. 16A shows a state of the upper electrode before annealing, and FIG. 16B shows a state of the upper electrode after annealing performed in a forming gas at 430.degree. C. for one hour. In addition, the capacitor structure is composed of a lower electrode layer made from Pt, a ferroelectric thin film made from Bi.sub.x St.sub.y Ta.sub.2 O.sub.d expressed in the equation (2), and the upper electrode made from Pt. As will be apparent from comparison between the states shown in FIGS. 16A and 16B, the upper electrode after annealing in the forming gas is damaged. In addition, an upper electrode made from Ru or RuO.sub.2 is also damaged after annealing in the forming gas.
The occurrence of a damage in the upper electrode leads to short-circuit or reduction in the value of 2Pr of a P-E hysteresis loop of the ferroelectric thin film. In the worst case, the upper electrode is peeled from the capacitor thin film. FIG. 17 shows a difference between the P-E hysteresis loops of a ferroelectric thin film before and after annealing in a forming gas. The values of 2Pr and Ec.sup.+ and Ec.sup.- (critical field voltage) of the P-E hysteresis loops of the ferroelectric thin film before and after annealing are shown in Table 1. As will be apparent from Table 1, the value of 2Pr of the ferroelectric thin film after annealing in the forming gas is largely smaller than that of the ferroelectric thin film before annealing.
TABLE 1 ______________________________________ before annealing after annealing ______________________________________ 2Pr (.mu.C/cm.sup.2) 23.11 15.46 Ec.sup.+ (kV/cm) 43.45 55.46 Ec.sup.- (kV/cm) -47.52 -47.22 ______________________________________